The present invention relates to a technology which is effective when applied to a technology for embedding a diode in a semiconductor integrated circuit device (or semiconductor device) or a method of manufacturing the semiconductor integrated circuit device (or semiconductor device).
Japanese Unexamined Patent Publication No. 2006-310555 (Patent Document 1) or US Unexamined Patent Publication No. 2006-0244050 (Patent Document 2) discloses a technology which forms electrodes only over a P-type guard ring for a Schottky barrier diode embedded in a semiconductor integrated circuit device. In the publication, to avoid a reduction in breakdown voltage due to a defect in an isolation region, a space is provided between a P-type guard ring and a field insulating film in the isolation region.
Japanese Unexamined Patent Publication No. 2001-210839 (Patent Document 3) or the publication of U.S. Pat. No. 6,803,644 (Patent Document 4) discloses a technology which forms electrodes only over a deep peripheral impurity region, which is other than a region formed with a PN junction, for a Zener diode embedded in a semiconductor integrated circuit device.
[Patent Document 1]
    Japanese Unexamined Patent Publication No. 2006-310555[Patent Document 2]    US Unexamined Patent Publication No. 2006-0244050[Patent Document 3]    Japanese Unexamined Patent Publication No. 2001-210839[Patent Document 4]    U.S. Pat. No. 6,803,644